검색결과 : 9건
| No. | Article |
|---|---|
| 1 |
A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology Morin P, Maitrejean S, Allibert F, Augendre E, Liu Q, Loubet N, Grenouillet L, Pofelski A, Chen KG, Khakifirooz A, Wacquez R, Reboh S, Bonnevialle A, le Royer C, Morand Y, Kanyandekwe J, Chanemougamme D, Mignot Y, Escarabajal Y, Lherron B, Chafik F, Pilorget S, Caubet P, Vinet M, Clement L, Desalvo B, Doris B, Kleemeier W Solid-State Electronics, 117, 100, 2016 |
| 2 |
Mushroom-free selective epitaxial growth of Si, SiGe and SiGe:B raised sources and drains Hartmann JM, Benevent V, Barnes JP, Veillerot M, Lafond D, Damlencourt JF, Morvan S, Previtali B, Andrieu F, Loubet N, Dutartre D Solid-State Electronics, 83, 10, 2013 |
| 3 |
Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drain formation in advanced 20 nm n-type field effect transistor devices Loubet N, Adam T, Raymond M, Liu Q, Cheng KG, Sreenivasan R, Reznicek A, Khare P, Kleemeier W, Paruchuri V, Doris B, Sampson R Thin Solid Films, 520(8), 3149, 2012 |
| 4 |
Effect of Thermal Annealing on Carbon in In-situ Phosphorous-Doped Si1-xCx films Adam T, Loubet N, Reznicek A, Paruchuri V, Sampson R, Sadana D Thin Solid Films, 520(8), 3155, 2012 |
| 5 |
Thin-film devices for low power applications Monfra S, Fenouillet-Beranger C, Bidal G, Boeuf F, Denorme S, Huguenin JL, Samson MP, Loubet N, Hartmann JM, Campidelli Y, Destefanis V, Arvet C, Benotmane K, Clement L, Faynot O, Skotnicki T Solid-State Electronics, 54(2), 90, 2010 |
| 6 |
Gate-all-around technology: Taking advantage of ballistic transport? Huguenin JL, Bidal G, Denorme S, Fleury D, Loubet N, Pouydebasque A, Perreau P, Leverd F, Barnola S, Beneyton R, Orlando B, Gouraud P, Salvetat T, Clement L, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 54(9), 883, 2010 |
| 7 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |
| 8 |
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution Bidal G, Loubet N, Fenouillet-Beranger C, Denorme S, Perreau P, Fleury D, Clement L, Laviron C, Leverd F, Gouraud P, Barnola S, Beneyton R, Torres A, Duluard C, Chapon JD, Orlando B, Salvetat T, Grosjean M, Deloffre E, Pantel R, Dutartre D, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 53(7), 735, 2009 |
| 9 |
Selective etching of Si(1-x)Ge(x) versus Si with gaseous HCl for the formation of advanced CMOS devices Loubet N, Kormann T, Chabanne G, Denorme S, Dutartre D Thin Solid Films, 517(1), 93, 2008 |