화학공학소재연구정보센터
Solid-State Electronics, Vol.53, No.7, 735-740, 2009
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution
This work proposes a planar fully depleted "folded" technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide ultra thin body and buried oxide (UTB2) devices with improved drive current I-on for a given designed footprint W-design when scaling the device width. We compare the fabrication and electrical behavior between < 1 1 0 > channel, i.e. 0 degrees-rotated wafer, and < 1 0 0 > channel, i.e. 45 degrees-rotated wafer, for the same (1 0 0) surface orientation. (C) 2009 Elsevier Ltd. All rights reserved.