검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology Morin P, Maitrejean S, Allibert F, Augendre E, Liu Q, Loubet N, Grenouillet L, Pofelski A, Chen KG, Khakifirooz A, Wacquez R, Reboh S, Bonnevialle A, le Royer C, Morand Y, Kanyandekwe J, Chanemougamme D, Mignot Y, Escarabajal Y, Lherron B, Chafik F, Pilorget S, Caubet P, Vinet M, Clement L, Desalvo B, Doris B, Kleemeier W Solid-State Electronics, 117, 100, 2016 |
| 2 |
Thin-film devices for low power applications Monfra S, Fenouillet-Beranger C, Bidal G, Boeuf F, Denorme S, Huguenin JL, Samson MP, Loubet N, Hartmann JM, Campidelli Y, Destefanis V, Arvet C, Benotmane K, Clement L, Faynot O, Skotnicki T Solid-State Electronics, 54(2), 90, 2010 |
| 3 |
Gate-all-around technology: Taking advantage of ballistic transport? Huguenin JL, Bidal G, Denorme S, Fleury D, Loubet N, Pouydebasque A, Perreau P, Leverd F, Barnola S, Beneyton R, Orlando B, Gouraud P, Salvetat T, Clement L, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 54(9), 883, 2010 |
| 4 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |
| 5 |
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution Bidal G, Loubet N, Fenouillet-Beranger C, Denorme S, Perreau P, Fleury D, Clement L, Laviron C, Leverd F, Gouraud P, Barnola S, Beneyton R, Torres A, Duluard C, Chapon JD, Orlando B, Salvetat T, Grosjean M, Deloffre E, Pantel R, Dutartre D, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 53(7), 735, 2009 |