검색결과 : 9건
| No. | Article |
|---|---|
| 1 |
Study of line-TFET analog performance comparing with other TFET and MOSFET architectures Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 128, 43, 2017 |
| 2 |
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism Martino MD, Neves F, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 112, 51, 2015 |
| 3 |
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, Loo R, Groeseneken G, Huyghebaert C Solid-State Electronics, 83, 50, 2013 |
| 4 |
Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs Vandooren A, Leonelli D, Rooyackers R, Arstila K, Groeseneken G, Huyghebaert C Solid-State Electronics, 72, 82, 2012 |
| 5 |
Drive current enhancement in p-tunnel FETs by optimization of the process conditions Leonelli D, Vandooren A, Rooyackers R, De Gendt S, Heyns MM, Groeseneken G Solid-State Electronics, 65-66, 28, 2011 |
| 6 |
Coupling effects and channels separation in FinFETs Dauge F, Pretet J, Cristoloveanu S, Vandooren A, Mathew L, Jomaah J, Nguyen BY Solid-State Electronics, 48(4), 535, 2004 |
| 7 |
Comparison of raised source/drain versus raised extension in ultra-thin body, fully-depleted-SOI, including effects of BEOL via capacitances Egley JL, Vandooren A, Winstead B, Verret E, Workman C, White B, Nguyen BY Solid-State Electronics, 48(9), 1607, 2004 |
| 8 |
A systematic investigation of the degradation mechanisms in SOI n-channel LD-MOSFETs Vandooren A, Cristoloveanu S, Conley JF, Mojarradi M, Kolawa E Solid-State Electronics, 47(9), 1419, 2003 |
| 9 |
Hall effect measurements in double-gate SOI MOSFETs Vandooren A, Cristoloveanu S, Flandre D, Colinge JP Solid-State Electronics, 45(10), 1793, 2001 |