We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunnel Field Effect Transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (MuGFETs) technology compatible with standard CMOS processing. Firstly, we assess the impact of the gate oxide thickness on the tunneling performance. Secondly, we investigate the effect of the doping concentration and profile by implementing different doping conditions. Thirdly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). In case of SPER anneal a record drive current of 46 mu A/mu m at V(DD) of -1.2 V and I(OFF) of 5 pA/mu m for Si pTFETs is reported. The enhanced current is given by the position of the suicide at the n+ side close to the gate. Silicide engineering opens a new opportunity to optimize tunnel devices. (C) 2011 Elsevier Ltd. All rights reserved.