| 1 |
Simulation on Optimum Doping Levels in Si Solar Cells
Choe KS
Korean Journal of Materials Research, 30(10), 509, 2020 |
| 2 |
Simulation Study of Front-Lit Versus Back-Lit Si Solar Cells
Choe KS
Korean Journal of Materials Research, 28(1), 38, 2018 |
| 3 |
Simulated Study on the Effects of Substrate Thickness and Minority-Carrier Lifetime in Back Contact and Back Junction Si Solar Cells
Choe KS
Korean Journal of Materials Research, 27(2), 107, 2017 |
| 4 |
A Simulated Study of Silicon Solar Cell Power Output as a Function of Minority-Carrier Recombination Lifetime and Substrate Thickness
Choe KS
Korean Journal of Materials Research, 25(9), 487, 2015 |
| 5 |
Simulated Optimum Substrate Thicknesses for the BC-BJ Si and GaAs Solar Cells
Choe KS
Korean Journal of Materials Research, 22(9), 450, 2012 |
| 6 |
0.1 μm SOI-MOSFET의 적정 채널도핑농도에 관한 시뮬레이션 연구
최광수
Korean Journal of Materials Research, 18(5), 272, 2008 |
| 7 |
Electrical characteristics and simulations of self-switching-diodes in SOI technology
Farhi G, Saracco E, Beerens J, Morris D, Charlebois SA, Raskin JP
Solid-State Electronics, 51(9), 1245, 2007 |
| 8 |
Towards the fabrication and measurement of high sensitivity SiC-UV detectors with oxide ramp termination
Brezeanu G, Godignon P, Dimitrova E, Raynaud C, Planson D, Mihaila A, Udrea F, Milian J, Amaratunga G, Boianceanu C
Materials Science Forum, 457-460, 1495, 2004 |
| 9 |
Simulation and fabrication of high-voltage 4H-SiC diodes with multiple floating guard ring termination
Sheridan DC, Niu G, Merrett JN, Cressler JD, Ellis C, Tin CC, Siergiej RR
Materials Science Forum, 338-3, 1339, 2000 |
| 10 |
The effect of carbon content on the minority carrier lifetime in lattice-matched p(+)-Si/p-SiGeC/n-Si/n(+)-Si diodes
Shivaram R, Niu GF, Cressler JD, Croke ET
Solid-State Electronics, 44(3), 559, 2000 |
