검색결과 : 17건
| No. | Article |
|---|---|
| 1 |
Analytical modeling of capacitances in tunnel-FETs including the effect of Schottky barrier contacts Farokhnejad A, Schwarz M, Horst F, Iniguez B, Lime F, Kloes A Solid-State Electronics, 159, 191, 2019 |
| 2 |
A compact explicit DC model for short channel Gate-All-Around junctionless MOSFETs Lime F, Avila-Herrera F, Cerdeira A, Iniguez B Solid-State Electronics, 131, 24, 2017 |
| 3 |
Crystalline-like temperature dependence of the electrical characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors Estrada M, Hernandez-Barrios Y, Cerdeira A, Avila-Herrera F, Tinoco J, Moldovan O, Lime F, Iniguez B Solid-State Electronics, 135, 43, 2017 |
| 4 |
A quantum wave based compact modeling approach for the current in ultra-short DG MOSFETs suitable for rapid multi-scale simulations Hosenfeld F, Horst F, Iniguez B, Lime F, Kloes A Solid-State Electronics, 137, 70, 2017 |
| 5 |
A simple compact model for long-channel junctionless Double Gate MOSFETs Lime F, Santana E, Iniguez B Solid-State Electronics, 80, 28, 2013 |
| 6 |
Modeling of low frequency noise in FD SOI MOSFETs El Husseini J, Martinez F, Valenza M, Ritzenthaler R, Lime F, Iniguez B, Faynot O, Le Royer C, Andrieu F Solid-State Electronics, 90, 116, 2013 |
| 7 |
Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model Darbandy G, Lime F, Cerdeira A, Estrada M, Garduno SI, Iniguez B Solid-State Electronics, 75, 22, 2012 |
| 8 |
A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation Lime F, Ritzenthaler R, Ricoma M, Martinez F, Pascal F, Miranda E, Faynot O, Iniguez B Solid-State Electronics, 57(1), 61, 2011 |
| 9 |
3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors Ritzenthaler R, Lime F, Faynot O, Cristoloveanu S, Iniguez B Solid-State Electronics, 65-66, 94, 2011 |
| 10 |
Analytical modeling of the gate tunneling leakage for the determination of adequate high-k dielectrics in double-gate SOI MOSFETs at the 22 nm node Darbandy G, Ritzenthaler R, Lime F, Garduno I, Estrada M, Cerdeira A, Iniguez B Solid-State Electronics, 54(10), 1083, 2010 |