검색결과 : 1건
| No. | Article |
|---|---|
| 1 |
Conduction barrier offset engineering for DRAM capacitor scaling Pesic M, Knebel S, Cho K, Jung C, Chang J, Lim H, Kolomiiets N, Afanas'ev VV, Mikolajick T, Schroeder U Solid-State Electronics, 115, 133, 2016 |
| No. | Article |
|---|---|
| 1 |
Conduction barrier offset engineering for DRAM capacitor scaling Pesic M, Knebel S, Cho K, Jung C, Chang J, Lim H, Kolomiiets N, Afanas'ev VV, Mikolajick T, Schroeder U Solid-State Electronics, 115, 133, 2016 |