| 1 |
Energy capability improvement of power DMOS transistors operating in pulsed conditions
Costachescu D, Pfost M
Solid-State Electronics, 103, 140, 2015 |
| 2 |
Comparisons of hot-carrier degradation behavior in SOI-LIGBT and SOI-LDMOS with different stress conditions
Liu SY, Sun WF, Qian QS, Zhu J
Solid-State Electronics, 54(12), 1598, 2010 |
| 3 |
Achieving accuracy in modeling the temperature coefficient of threshold voltage in MOS transistors with uniform and horizontally nonuniform channel doping
d'Alessandro V, Spirito P
Solid-State Electronics, 49(7), 1098, 2005 |
| 4 |
Self-aligned short-channel vertical power DMOSFETs in 4H-SiC
Matin M, Saha A, Cooper JA
Materials Science Forum, 457-460, 1393, 2004 |
| 5 |
Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test
Pinardi K, Heinle U, Bengtsson S, Olsson J, Colinge JP
Solid-State Electronics, 48(7), 1119, 2004 |
| 6 |
Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts
Pinardi K, Heinle U, Bengtsson S, Olsson J, Colinge JP
Solid-State Electronics, 46(12), 2105, 2002 |
| 7 |
Monolithic integration of low voltage devices in 3 kV planar MOS controlled power devices
Ngw CK, Sweet M, Bose JVSC, Spulber O, King NL, Vershinin K, De Souza MM, Narayanan EMS
Solid-State Electronics, 45(1), 127, 2001 |
