| 학회 | 한국재료학회 |
| 학술대회 | 2014년 가을 (11/27 ~ 11/28, 대전컨벤션센터) |
| 권호 | 20권 2호 |
| 발표분야 | A. 전자/반도체 재료(Electronic and Semiconductor Materials) |
| 제목 | Lateral growth induced SiGe/Si bi-layer for vertical channel in VNAND |
| 초록 | Vertical NAND (VNAND) flash memory has been developed to overcome the scaling limit of conventional two-dimensional flash memory.1,2 Poly-crystalline Si thin film is used as a vertical channel in VNAND and the channel is formed by solid phase crystallization (SPC) technique. When the number of stacked NAND layers is increased for high-bit densities, the vertical channel string current is expected to be degraded due to potential barriers in the band structure formed by grain boundaries. Therefore, large-grained Si vertical channel is required for VNAND. Recently, we have reported advanced SPC3 to obtain a high quality poly-crystalline Si vertical channel by using SiGe/Si bi-layer structure. In that experiment, the crystallization behavior was observed through in situ transmission electron microscopy (TEM) measurement in real time. During the crystallization, the underlying Si layer shows solid-phase epitaxy-like growth on the crystallized SiGe as a seed. The SiGe microstructure is critical because the underlying Si layer follows the grain boundaries of SiGe. Therefore, the large-grained SiGe layer is desired. In this experiment, we have attempted SiGe lateral growth to introduce large-grained SiGe microstructure. The lateral growth method is extensively utilized to obtain larger grains for several the crystallization techniques such as selective nucleation4, super lateral growth5 and metal-induced lateral growth6. We have used a two-step annealing process, low temperature annealing followed by high temperature one. To introduce larger SiGe grains, both SiGe lateral growth and Si growth suppression should be realized in the low temperature annealing. The Si and Si1-xGex layers were sequentially deposited on silicon dioxide on Si substrate by a using low-pressure chemical vapor deposition system. The annealing was performed in a conventional furnace system in nitrogen ambient. The annealed samples were characterized by cross-sectional TEM measurement. The in situ cross-section TEM measurement during the annealing was also carried out to directly observe the crystallization behavior of the bi-layer structure. References 1. H. Tanaka et al., VLSI Technol. 2007, 14–15. 2. J. Jang et al., VLSI Technol. 2009, 192–193. 3. S. Lee et al., APL Mat. 2, 076106 (2014). 4. N. Yamaguchi et al., J. Appl. Phys. 75, 3235 (1994). 5. J. S. Im et al., Appl. Phys. Lett. 63, 1969 (1993). 6. J. Park et al. Appl. Phys. Lett. 91, 143107 (2007). |
| 저자 | Sangsoo Lee1, Yong-Hoon Son1, Yongjo Park2, Kihyun Hwang3, Yoo Gyun Shin1, Euijoon Yoon2 |
| 소속 | 1Seoul National Univ., 2Samsung Electronics Co., 3Ltd. |
| 키워드 | SiGe; Si; SPC; TEM; VNAND |
