| 초록 |
The device features scale down led to the replacement of Al/SiO2 with Cu/low-k for back end interconnects, in order to decrease the RC delay. To create the vias and trenches in the copper interconnect was employed to the damascene structure. In the process which fabricated to the damascene integration, the etch treatment by plasma process in the dielectric typically leaves post etch residues (PER), such as the copper contaminations on the dielectric sidewalls and the formation of copper oxides in the bottom of vias. The cleaning formulations requires that can remove copper oxide selectively without corroding and etching the dielectric. Many commercially available semi-aqueous and all aqueous formulations claim to meet these criteria. We have been evaluated to study the effects of pH in the several aqueous solutions for the application of post-etch residue (PER) removal, which is required after plasma etching and the subsequent ashing process. |
