We present optimization of electrochemical etching process in p-type silicon because the formation of p-type ordered porous silicon or silicon wire arrays has not been well documented compared with n-type ones. In order to prepare and fabricate p-type silicon wire arrays without pore walls for silicon-based solar cell application, the effect of electrochemical etching process parameters, such as concentration of electrolyte, wafer resistivity, distance between counter electrode and silicon wafer, and applied current density and etching time, should be investigated. As a result, the morphology and aspect ratio (height/diameter) of silicon wires are observed and the behavior of electrochemical etching of silicon is studied. Finally, the vertically ordered silicon wire arrays are fabricated uniformly under the optimized etching conditions and the process is very reproducible. Crown Copyright (C) 2010 Published by Elsevier B. V. All rights reserved.