CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO2 STI patterned 200 mm Si (001) wafers. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.041204jes] All rights reserved.