A multiple-input/multiple-output graph reversal technique is developed and applied to the design of parallel control (and signal processing) architectures using systolic arrays as a design example. Using this method, it is possible to develop novel architectures with, in feedback central applications, the essential property of short latency, Further, it can also be used to expand existing architectures at both array and cell levels. A systematic method for verifying the transfer function (or transfer-function matrix in the multivariable case) which is easy to use and requires no manual iteration is developed. In developing this method, the well known ABCD transmission matrix description of an analogue network is extended to the digital domain. Some areas for short to medium term further research/development are briefly noted.