This study reports the development of InAs-channel MOSFETs using PECVD-deposited SiO2 gate dielectrics. Arsenic capping and desorption are applied to as-grown wafers to prevent the formation of native oxides before the gate dielectrics are then deposited. We believe that increased hole confinement in a layer structure effectively suppresses the impact ionization effect, and an output conductance as 18 mS/mm at a drain bias of 2 V is demonstrated. A 2 mu m-gate-length device exhibits dc performances of I-DSS = 154 mA/mm and g(m) = 189 mS/mm, and rf performances of f(T) = 14.5 GHz and f(MAX) = 24 GHz. The InAs-channel MOS-FET has potential for application in high frequency circuit devices. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3594098] All rights reserved.