In this paper we present an overview of partially depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a "high performance per watt" figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power-efficient designs. These techniques have been developed, applied and optimized for 45 nm SOI volume manufacturing at GLOBAL-FOUNDRIES in Dresden. To enable further transistor scaling to 32 nm design rules, High K Metal Gate (HKMG) technology is the key, Different HKMG integrations as well as future strained Si technologies, like strained silicon directly bonded on 501, and embedded Si:C are discussed. (C) 2009 Elsevier Ltd. All rights reserved.