Formation of poly-Si thin-film transistor (TFT) by large-angle-tilt-implantation of dopant through gate sidewall spacer (LATITS) has been proposed. By this LATITS scheme, the lightly doped drain (LDD) region under the oxide spacer is formed by tilt implantation of dopant through spacer and then the n(+) source/drain region is formed via using the same mask layer while the CMOS integration. The resultant on-state currents are comparable for both the conventional LDD scheme and the LATITS scheme. In addition, the LATITS scheme can even cause a smaller leakage current than the LDD scheme at high negative gate voltage, due to less gate-drain overlap region. By the LATITS scheme with proper tilt implantation energy, dose and angle, poly-Si TFT devices with an on/off current ratio above eight orders may be achieved with fewer process steps, as compared to the conventional LDD scheme. (C) 2009 Elsevier Ltd. All rights reserved.