This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) structures. The pattern dependency behavior of the growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by the gas depletion theory of the growth species in the stationary boundary layer over the water. Control of the SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer. (c) 2009 The Electrochemical Society. [DOI: 10.1149/1.3049842] All rights reserved.