In this article, the authors investigate the formation and removal of resist residues with the main objective to improve the reliability of transistor gate fabrication. Device performance is strongly dependent on the quality of metal contacts and the interface between gate metal and substrates. Reliable transistor fabrication becomes increasingly difficult as transistor dimensions shrink. Residual resist layers can become significant if wet or dry etching steps are required for gate recessing, e.g., for high electron mobility transistors or the removal of thin oxide layers in III-V metal oxide semiconductor field effect transistor fabrication. They observe two sorts of residual resist layers in polymethyl methacrylate (PMMA): exposed and nonexposed. Exposed residuals have been observed by many groups in electron beam exposed and developed regions of PMMA. In this article, they show that the observed granularity lies on top of a continuous residual film and consider this effect on gate fabrication. They also present evidence of a nonexposed residual layer observed in regions of unexposed resist which have been subject to a standard solvent based resist strip and cleaning procedure. They further demonstrate that CV measurement techniques can be used to detect the presence of residual layers of resist.