In this contribution, the authors analyze first results about the impact of electrical stress on triple gate SOI nFinFETs with metal gate (TiN) and SiON or HfO2 gate dielectrics, with particular emphasis on the roles of fin width and back gate polarization. A similar progressive degradation of the characteristics is observed for both types of gate dielectric devices. An increasing degradation with reducing fin width is observed for a certain range of wide fin devices (between about 3 mu m and 130 nm), which could be attributed to a higher contribution of corner effects or lower quality side surfaces. However, the narrowest triple gate FinFETs with geometries around the nominal values of this technology (70 nm long and 30 nm wide fins) show reduced degradation with electrical stress. Under the studied experimental conditions, no clear impact on device degradation is observed for different back gate bias conditions applied during electrical stress. A typical dielectric breakdown mode characterized by a sudden decrease in drain current, accompanied by a significant increase in front gate current, is observed quite often in devices subjected to strong or long stress conditions. From the analysis of the encountered postbreakdown source/drain asymmetries, it is inferred that most of such catastrophic failures under V-FG=V-D stress regime may correspond to gate-to-source dielectric breakdown. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3025883]