This article highlights some aspects associated with the fabrication of stacked nanowire metal oxide semiconductor field effect transistors (MOSFETs) and more precisely the active area conception. These novel architectures, with gate-all-around or independent gates (Phi FET), are promising solutions to improve electrostatic control with high on-current (I-on) and to reduce power consumption for sub-32-nm transistors. Their fabrication is highly complex regarding lithography and etching. For this study, stacked nanowires were achieved by using hybrid lithography (e-beam/deep ultraviolet) combined with anisotropic and isotropic etchings of a Si/SiGe multilayer to form suspended silicon nanowires. Therefore, we needed high aspect ratio resist features in order to perform the anisotropic etch of the Si/SiGe multilayer (thickness: 250 nm). For this purpose, we compared two ways to pattern the sub-32-nm silicon stacked nanowires. On one hand, a resist trimming was performed on thick large critical dimension patterns before etching. On the other hand, an amorphous carbon hard mask combined with a thin oxide capping layer was added on our structure to suppress resist thickness limitations and extend high resolution lithography capabilities. The best results so far were obtained using the first of these two techniques, which yielded 25 nm stacked nanowire MOSFETs.