Because of the ever-decreasing feature size in modern photolithography, the complexity of semiconductor patterns continues to increase dramatically, resulting in prolonged tape-out times. The most time-consuming process in the tape-out flow is model-based optical proximity correction (OPC), which employs two components: a process model and a recipe. The process model predicts how the manufacturing process will behave at a given location on a wafer, whereas the recipe controls how the model information is used to modify the pattern. The recipe uses the model multiple times for each fraction of a polygon in a semiconductor device pattern, resulting in hundreds of billions of complex and time-consuming calculations. To analyze a design-team-drawn device pattern for semiconductor manufacturability, these tape-out calculations need to be performed. This study is designed to reduce the semiconductor pattern manufacturing analysis time by creating an OPC recipe simulation in the process model for use in rapid analysis and filtering of the drawn semiconductor design. In this study, the authors introduce a method of calculating the OPC effect by modifying the optical model, which is equivalent to transferring the OPC effect into the process model. (C) 2008 American Vacuum Society. [DOI: 10.1116/1.2981085]