Developing alternative high dielectric constant (k) materials for use as gate dielectrics is essential for continued advances in conventional inorganic CMOS and organic thin film transistors (OTFTs). Thicker films of high-k materials suppress tunneling leakage currents while providing effective capacitances comparable to those of thin films of lower-k materials. Self-assembled monolayers (SAMS) and multilayers offer attractive options for alternative OTFT gate dielectrics. One class of materials, organosilane-based self-assembled nanodielectrics; (SANDS), has been shown to form robust films with excellent insulating and surface passivation properties, enhancing both organic and inorganic TFT performance and lowering device operating voltages. Since gate leakage current through the dielectric is one factor limiting continued TFT performance improvements, we investigate here the current (voltage, temperature) (I (V,T)) transport characteristics of SAND types II (pi-conjugated layer) and III (sigma-saturated + pi-conjugated layers) in Si/native SiO2/SAND/Au metal-insulator-metal (MIS) devices over the temperature range -60 to + 100 degrees C. It is found that the location of the pi-conjugated layer with respect to the Si/SiO2 substrate surface in combination with a saturated alkylsilane tunneling barrier is crucial in controlling the overall leakage current through the various SAND structures. For small applied voltages, hopping transport dominates at all temperatures for the pi-conjugated system (type II). However, for type III SANDS, the sigma- and pi-monolayers dominate the transport in two different transport regimes: hopping between +25 degrees C and +100 degrees C, and an apparent switch to tunneling for temperatures below 25 degrees C. The sigma-saturated alkylsilane tunneling barrier functions to reduce type III current leakage by blocking injected electrons, and by enabling bulk-dominated (Poole-Frenkel) transport vs electrode-dominated (Schottky) transport in type II SANDs. These observations provide insights for designing next-generation self-assembled gate dielectrics, since the bulk-dominated transport resulting from combining sigma- and pi-layers should enable realization of gate dielectrics with further enhanced performance.