In this paper, a post-CMOS selective grown porous silicon (SGPS) technique is proposed to achieve high-performance integrated inductor and effective isolation. The inductors and isolation structures are fabricated in standard CMOS process and then this post-CMOS SGPS technique is carried out to greatly improve the performances of inductors and crosstalk isolation. For a 4.5 nH inductor fabricated in standard CMOS process, an over 100% increase (from 4.8 to 9.7) in peak Q-factor and an about 200% increase (from 4 GHz to 12 GHz) in resonance frequency are obtained. Furthermore, a thick SGPS trench for crosstalk isolation has been formed and about 20 dB improvement in substrate isolation is achieved. These results demonstrate that the post-CMOS SGPS technique is very promising for RFIC applications. (C) 2007 Elsevier Ltd. All rights reserved.