SiC high power rf devices are slated to replace Si devices to enhance system performance and to reduce overall cost. A common SiC rf bipolar junction transistor (BJT), fabrication process includes homoepitaxial growth of differently doped layers followed by several dry etching steps. In this article the authors will focus on two critical etch processes evaluated on 2 in. SiC wafers. The first process is a deep (> 5 mu m) etch for electrical isolation between devices. The second process is a shallow (< 0.3 mu m) precise etch down to the base layer. They present details on a novel etch process for SiC rf BIT fabrication process based on the combination of reactive ion etch (RIE), sheet conductance measurements, and oxidation. The RIE parameters were optimized resulting in smooth etched surfaces and sufficient etch depth uniformity of < 8% for shallow etch and, < 2% for deep etch across 2 in. SiC wafers. Their etching process provides a precision (+/- 10 nm) emitter etch to the emitter-base junction, even when the actual epitaxial layer thicknesses are different than expected. This method was also used to measure the emitter layer thickness and resistivity uniformity across different wafers and lots. The results of these measurements will be presented. Furthermore, precise etching of the emitter epitaxial layer results in improved rf performance of the BIT through optimization of the base sheet resistance. Using this RIE process, the authors successfully fabricated several lots of 50 W ultrahigh frequency SiC BJTs with a dc probe yield larger than 90%. (c) 2007 American Vacuum Society.