In this paper we demonstrate a physical two-dimensional hydrodynamic (2D HD) model, which simulates the DC and AC characteristics of vertically and laterally scaled InP/InGaAs(P) type I double heterojunction bipolar transistors (DHBTs) with state-of-the-art accuracy when compared to experimental data. For the first time, a physical model clearly shows good agreement between simulated and measured circuit data, for example the gate delay of current mode logic (CML) or emitter coupled logic (ECL) ring oscillators of laterally and vertically scaled devices. The deviation of the simulated gate delays of these digital circuits is smaller than 10%. Additionally, the model successfully predicts the circuit performance of experimental frequency dividers and multiplexers. This experimentally verified model can be used to predict and optimize AC and switching characteristics of future generations of aggressively downscaled DHBTs and is a significant advancement in the art of physical and scalable DHBT and circuit modeling. We demonstrate that optimized type I DHBTs approach bit rates towards 235 Gb/s with realistic scaling parameters in the near future. (C) 2006 Elsevier Ltd. All rights reserved.