The scaling of CMOS technology to 100 nm and below and the endless pursuit of higher operating frequencies drives the need to accurately model effects such as gate leakage and the deterioration of transport characteristics that dominate at those feature sizes and frequencies. Current modeling techniques are frequency limited and require different models for different frequency ranges in order to achieve accuracy goals. In the foundry world, high frequency models are typically empirical in nature and significantly lag their low frequency counterparts in terms of availability. This tends to slow the adoption of new foundry technologies for high performance applications such as extremely high data rate serializer/deserializer (SERDES) transceiver cores. However, design cycle time and time to market while transitioning between technology nodes can be reduced by incorporating a re-usable, industry-standard model. This work proposes such a model for device gate impedance that is simulator-friendly, compact, frequency-independent, and relatively portable across technology nodes. This semi-empirical gate impedance model is based on depletion in the poly-silicon gate electrode. The model performs accurately over 200 MHz-20 GHz at different bias conditions and widths and has been verified by measured data in three technology nodes. The model and model parameter behavior are consistent across technology nodes thereby enabling re-usability and portability. (c) 2006 Elsevier Ltd. All rights reserved.