16 Mb 2-transistor (2T)-SONOS flash memories have been processed in a 0.18 mu m CMOS technology. The 2T NOR architecture allows fast random access and low power program and erase by tunneling. Also, negative erased threshold voltages enable low voltage read without boosting. This paper shows the operation and reliability aspects of 2T N-type SONOS memories: endurance, retention and read disturb. A further reduction in read voltage is demonstrated by using P-type SONOS and makes it even possible to operate the devices with a symmetric threshold voltage (V-T) window around 0 V. In this case, read disturb is completely avoided and the advantages of the 2T NOR architecture are fully used, meaning fast random access and real low power operation. Besides SONOS embedded flash memories, also the reliability of devices with either the top layer or trapping layer made of the high-K materials HfO2 or HfSiON have been investigated. The memories with a high-K top layer are indicated by SHINOS (Silicon-High-K-Nitride-Oxide-Silicon). A strong gain in program/erase efficiency can be obtained for SHINOS compared with SONOS memories. The SHINOS devices show good endurance and retention. The retention of the SHINOS devices can be considerably improved by trading-off the improved program/erase efficiency with a thicker bottom oxide. (c) 2005 Elsevier Ltd. All rights reserved.