The purpose of this article is to briefly review the recent progress in terms of mobility and drive current enhancements achieved in strained-Si n- and p-metal oxide semiconductor field effect transistors (MOSFETs). Strained Si MOSFETs are potential candidates for future high performance CMOS applications, and the electron mobility enhancement factor over 3 and saturation drain current enhancement over 90% compared to bulk Si CMOS have been reported for surface channel device. The hole mobility enhancement factor over 2 has been achieved for the surface channel strained Si device while that for the buried channel compressively strained SiGre is reported to be over 5. Techniques for designing channel architectures of heterostructure CMOS (HCMOS) devices are discussed. The challenges in device design, thermal budget optimisation, SALICIDE issues and integration of different modules are addressed. Crown Copyright (C) 2004 Published by Elsevier Ltd. All rights reserved.