A new selective strained Si process has been developed incorporating thin (similar to200 nm) strain-relaxed SiGe buffers. For the first time. strained silicon and strain relaxed buffer can be deposited selectively on the active area in between preformed shallow trench isolation structures. The combination of in situ chemical vapor etch and selective epitaxial re-growth allows the implementation of strained Si layers in CMOS flow, without the need of chemical mechanical planarisation and without modifications of the standard STI process. NMOSFETs fabricated in selective Strained Si layers on 20% Ge strain relaxed buffers show a carrier mobility increase of similar to50% compared to Si reference devices. The results of first non-optimized devices demonstrate the potential of this strained Si fabrication scheme. (C) 2004 Published by Elsevier Ltd.