Scaling of pseudomorphic high electron mobility transistors (PHEMTs) into deep sub-100 nm dimensions can dramatically improve their performance. However, the reduction in the channel carrier density of the scaled devices with a single delta doped layer (DDL) has a detrimental effect on the drain current and consequently on the power handling capability. The linearity of the scaled transistors also deteriorates. These negative aspects of the scaling can be compensated with an additional DDL introduced into the device structure. We employ Monte Carlo device simulations to study the effect of two possible placements of the second DDL on the performance of aggressively scaled PHEMTs. The placement of the second DDL below the channel increases the drive current and linearity but does not improve the transconductance. The placement of the second DDL above the original one increases the current and improves the transconductance by up to approximately 45% but does not improve linearity. In order to understand the breakdown limitations of the scaled devices both the impact ionization and the gate tunnelling currents are included in the Monte Carlo simulator and monitored in the simulations. (C) 2004 Elsevier Ltd. All rights reserved.