We propose a new structure, asymmetric gate stack (ASYMGAS)-MOSFET and its 2-D analytical model. There is two-layer gate stack oxide near the drain and single gate oxide near the source. The model predicts a step function profile in the potential along the channel, which ensures reduced DIBL. In ASYMGAS-MOSFET, the average electric field in the channel is enhanced, and therefore electron velocity, near the source, which improves the overall carrier transport efficiency. The results so obtained are verified using a two-dimensional device simulator, ATLAS, over a wide range of device parameters and bias conditions. Good agreement is obtained for channel lengths down to 0.15 mum. Thus, confirming the validity of our model. (C) 2003 Published by Elsevier Ltd.