Silicon-on-insulator (SOI) is emerging as a strong technology candidate for low-power high-performance applications. In this work, based on experimental data, we review the fundamental aspects of leakage current in deep-submicron SOI CMOS technologies discussing the underlying physical mechanisms and their dependence with bias, temperature and operating frequency. These mechanisms and their evolution with technology scaling are compared to those of bulk CMOS. Subsequently, we evaluate the merits of parametric I-DDX testing techniques based on current monitoring when applied to these technologies. (C) 2003 Published by Elsevier Ltd.