This paper presents a novel non-volatile memory cell architecture (BipFlash), which improves remarkably injection efficiency over that obtained with conventional channel hot-electron programming. The cell concept is validated by means of numerical device simulations including accurate Monte Carlo analysis of hot carrier transport and injection in the floating gate. Design strategies to achieve optimum device performance and possible solutions for cell layout and array organization are also discussed. We show that the superior performance of BipFlash in terms of injection efficiency can be traded to achieve either very low voltage, low power or high-speed operation. (C) 2002 Elsevier Science Ltd. All rights reserved.