화학공학소재연구정보센터
Solid-State Electronics, Vol.45, No.10, 1763-1771, 2001
Design considerations for buried p-layers to suppress substrate-trapping effects in GaAs MESFETs
The effects of buried p-layers (BP-layers) on substrate-trap-induced frequency dispersion of drain conductance and drain lag in GaAs MESFETs have been analyzed. Our experiments show that the BP-layer concentration, profile, and configuration significantly affect its effectiveness in suppressing trap-induced low-frequency anomalies. BP-layer resistance should be low enough to enable fixing the electrostatic potential, which requires that the p-layers be partially neutralized. Our results can be explained by the self-backgating model and resistance measured for the BP-layers. However, while suppressing trap-induced phenomena, BP-layers may cause current transients at higher frequencies and degrade RF performance due to the charging and discharging of holes in the p-layer. This phenomenon is also investigated in detail.