The design of SiC planar and non-planar junction termination extension (JTE) structures are investigated through calibrated quasi-3D numerical simulation. JTE techniques are optimized with respect to breakdown voltage, area consumption, surface fields, and interface charge. Simulated JTE charge profiles predict near-ideal breakdown values with surface fields less than 60% of their bulk values, and show that the critical implant activation percentage can vary as much as 40%, with only 10% reduction in breakdown voltage for lightly doped blocking layers. These results are extended to unique multiple-zone JTE and mesa-JTE structures applicable to a wide range of planar and non-planar SiC power devices.