A 512 x 512 monolithic platinum silicide focal plane array with random line selection was proposed. The device was modified from an interline transfer charge couple device configuration by adapting a random line selected charge accumulation structure on a vertical register and four-tap readout structure on a horizontal register to achieve a high fill factor, high charge handling capacity, and high frame rate operation. An on-chip 9-bit decoder was used to select a particular line to transfer charges to their associated vertical charge coupled device (CCD) register. Accompanied with the vertical reset drain circuitry, 1-512 lines can be selected and read out by the vertical CCD registers. The dummy charges on the unselected lines are then transferred to the vertical CCD channel and dumped to the vertical reset drain. In this unique readout structure, a frame rate of upto 240 frames/s can be obtained to select 128 x 128 of Schottky barrier detectors for 5 MHz clock frequency operation. By changing the selection pattern on a 9-bit decoder, the device can be operated in either interlaced or non-interlaced format, and the charge integration time can be varied which results in variable exposure control. This architecture not only maintains the advantages of CCD structure for its low noise and excellent signal to noise ratio, but also provides readout capability of any portion of the array like MOS structure does.