Coupled process and device simulation is applied for the optimization of the doping in 0.18 mu m CMOS transistors. An advanced device architecture with a pocket type doping around the source/drain extensions was assumed to reduce the short channel effects. Two optimization targets were considered: the drain drive current at a fixed leakage current and a special figure of merit which characterizes the maximum switching frequency of the transistors. The method of response surface modeling was used to find the optimum conditions for the critical implantation steps which form the doping distribution in the active areas of the transistors. The simulation results show that an increase of the implantation dose of the source and drain extensions to values of 5 x 10(14)-10(15) cm(-2) improves both the drain drive current and the maximum switching frequency of the transistors. A three-dimensional simulation of the narrow channel transistors shows a significant non-uniformity in the lateral current distribution with the current maximum located at the edges of the active area of such transistors.