This paper describes a skew reducing strategy between the delay of replica model and that of the output-buffer along with variable external loads for a hierarchical delay-locked loop (DLL). The delay is initialized at the closest digitized value that is smaller than that of the output-buffer. Then, the precise open-loop based modification follows according to the detected accuracy of less than 100 ps in the vernier-scaled time-measurement circuit. The measured results of the test Si in a 0.35-mu m CMOS process reveal the validity of the proposed strategy. (c) 2005 Elsevier B.V. All rights reserved.