A process involving implantation mediated selective etching has been developed for source/drain elevation of metal-oxide-semiconductor devices. A 100 nm thick epitaxial silicon/polysilicon layer was formed on a patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700 degreesC. Samples were then implanted with 2 x 10(14)/cm(2) argon at 140 keV in the [100] channeling direction, followed by 1 min annealing at 420 degreesC. The polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits. (C) 2003 The Electrochemical Society.