Fabrication of low-temperature poly-Si thin film transistors with self-aligned graded lightly doped drain structure

Cheng HC; Lin CW; Cheng LJ; Tseng CH; Chang TK; Peng YC; Wang WT

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Electrochemical and Solid State Letters, Vol.5, No.1, G1-G3, 2002

Fabrication of low-temperature poly-Si thin film transistors with self-aligned graded lightly doped drain structure

Cheng HC, Lin CW, Cheng LJ, Tseng CH, Chang TK, Peng YC, Wang WT

A novel approach for fabricating low-temperature poly-Si (LTPS) thin film transistors (TFTs) with self-aligned graded lightly doped drain (LDD) structure was demonstrated. The self-aligned graded LDD structure was formed by side-etching the Al gate under the photoresist followed by excimer laser irradiation for dopant activation and lateral diffusion. The graded LDD poly-Si TFTs exhibited low-leakage-current characteristics without significantly sacrificing driving capability due to the graded dopant distribution in the LDD regions, in which the drain electric field could be reduced. The leakage current of 1 mum graded LDD UPS TFTs at Vds = 5 V and Vgs = -10 V could reach below 1 pA/mum, and the on/off current ratio at Vds = 5 V exceeded 10(7).