The current trend in-wafer-level three-dimensional integration is by copper-filled through-silicon vias (TSVs) which considerably minimize signal transmission time due to the short wiring length required to integrate vertically stacked chips. However, the present wire bonding technology widely used in peripheral integration of stacked chips cannot integrate TSV based chip stacks. This article describes the fabrication methodology of a thin film compliant interconnect re'feffed to as Smart Three Axis Compliant (STAC) interconnects which can be directly integrated onto TSV based chip stacks. These batch processed compliant interconnects are successfully fabricated utilizing microelectromechanical systems technology at the wafer level by magnetron sputtering oppositely stressed layers of TiW films. Once patterned and released, STAC interconnects easily achieve input/output counts of 10(4)/cm(2) or greater, making it suitable to be directly integrated onto through-silicon-via based chip stacks. (c) 2006 American Vacuum Society.