Silicon integrated sensors for thermomechanical stress measurement in very large scale integration (VLSI) has been studied extensively in recent years due to the increasing complexity of modem semiconductor devices. As the chip size has increased continuously to accommodate more functions in modern integrated circuits (IC) technology, the stress induced in it from packaging combined with self-heating becomes serious and may result in the device degradation, circuit malfunction, and even chip cracking. Therefore, for large VLSI devices safe operation, it is necessary to construct in situ thermomechanical stress sensors to control the spatial induced peak stress. In this article, a practical approach to the application of a gradient direction sensor (GDS) for thermomechanical stress prediction in microelectronic packaging is presented. The GDS method has been studied and analyzed for its applicability as inverse engineering problem. that is capable to detect the thermomechanical stress. This study uses a thermal heat sources emplacement approach to estimate and predict stress of wafer scale integration (WSI) chip junction. Hence, the geometrical coordinates of the investigated source can be obtained by applying the gradient direction sensors. Then finite element method will be used to build models to validate thermal peaks prediction by GDS method. This way, the possibilities to minimize the thermal peaks in the critical surface areas for ball grid array packaged WSI devices will be explored. Furthermore, in microelectronic, one of the primary roles of IC packaging is to provide structural stability for the VLSI chip. Hence, several considerations have guided our study for a judicious placement of different sensors. That will enable us to establish the most homogeneous thermomechanical cartography. Subsequently, other alternatives for heat sources placement or distribution that are capable in reducing the level of thermomechanical stress will be developed. (c) 2006 American Vacuum Society.