Recessed strained SiGe in the source/drain regions of planar Si pMOS devices is a well-known technique to enhance pMOS drive current. Both chemical vapour etching by HCl and conventional plasma etching have been proposed to define the source/drain recess. A comparison of both etching techniques brings us to the conclusion that isotropic plasma etching is the preferred etching technique. It avoids problems of facet formation during Si recess and allows better control of the lateral etching underneath the nitride spacer/gate oxide. Further, process optimization allows to minimize the variation in etch depth as function of window size. Surface damage caused during Si recess is removed by conventional cleans. High quality in situ doped SiGe layers, with boron concentrations up to similar to 4 x 10(20) cm(-3) are grown, without modification of our standard pre-epi thermal treatments. The success of our SiGe source/drain fabrication scheme is demonstrated by a 40% improvement in pMOS drive current in comparison to Si reference devices. (c) 2005 Elsevier B.V. All rights reserved.