Resist heating in high-voltage, high-throughput electron beam (e-beam) mask write is a significant source of critical dimension (CD) distortion. Excessive heating oil the reticle determines changes in resist sensitivity, which in turn cause significant CD variation. CD distortions on the reticle are replicated onto the wafer with increased magnitude as determined by the mask error enhancement factor (MEEF). As designs enter the sub-90 nm regime, CD variation has a significant impact on performance, performance variation, and product yield. Previous methods for reducing CD distortion include usage of lower e-beam current density, increased delays between electron flashes, and multipass writing. However, all of these methods lower mask writing throughput, which is increasingly becoming a limiting factor in semiconductor industry productivity. In this paper, we propose a novel method for minimizing CD distortion and maximizing mask writing throughput. By scheduling the writing of subfields, we perform simultaneous optimization of mask writing order and e-beam current density. We perform subfield scheduling h evaluating resist temperature of subfield orderings using a fast analytical temperature model. Simulation experiments show that the new subfield scheduling method can reduce the maximum resist temperature Lip to 12 degrees C over existing sequential writing methods with unchanged mask writing throughput, Alternatively. improved subfield scheduling can enable the use of higher beam current densities, leading to increased writing throughput without compromising CD control. (c) 2005 American Vacuum Society.