We developed a plasma doping (PLAD) technique which is appropriate for the nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) fabrications. Silicon-on-insulator (SOI) n-MOSFETs with a 50-nm-length metal gate and a 100-nm-channel width were successfully fabricated. The source and drain extensions (SDE) of SOI n-MOSFETs were formed using a plasma doping technique. The advantage of this process is the exclusion of additional activation annealing after introduction of impurity in SDE, which resulted in a laterally abrupt source/drain (S/D) junction profile. We can obtain a low sheet resistance by the PLAD technique and low damaged shallow junctions. A trigate structure SOI n-MOSFET with a gate length of 50 nm fabricated by high-temperature plasma doping revealed suppressed short-channel effects. (C) 2004 American Vacuum Society.