Negative bias temperature instabilities in hole channel metal-oxide-semiconductor field effect transistors (FETs) with thin SiO2/HfO2 gate stacks are investigated through the variation of the threshold voltage V-th of the devices during electrical stress. At low gate bias stress, the kinetics of V-th shifts can be explained by the buildup of positive charges at pre-existing defects. These defects have a low capture cross section, of the order of 10(-16) cm(2), that cannot be neutralized by electron injection in the gate stack and is partly annealed at 200degreesC, indicating that these defects could be hydrogen-related centers. At higher gate voltage stress, new defects are generated in the gate stack. It is suggested that these defects are interface defects (Si trivalent dangling bonds) and bulk defects induced by the trapping of released protons at strained Hf-O-Hf bridging bonds. (C) 2004 The Electrochemical Society.