Proper electrical functionality of devices is dependent on the proper insulation between active/passive areas and metal interconnect. Although low-k materials are gradually replacing SiO2 to achieve lower parasitic capacitance, they are Still SiO2-based. With the introduction of Cu as back-end metallization, the need for a barrier between insulator and metal arises, regardless of insulating materials. Ta has been established as a mainstream diffusion barrier in Cu interconnects. As device feature size shrinks, thickness of the Ta barrier also decreases. This raises a big concern on the effectiveness of thin, columnar Ta barriers in stopping the diffusion of Cu into SiO2, especially under simultaneous application of bias and thermal stresses. As the integrity of SiO2 is reliant on Ta to prevent Cu diffusion, bias-temperature stressing (BTS) would be a very suitable test to indirectly evaluate the Ta barrier through SiO2 integrity. In this study, the stability of a 5 nm Ta barrier is investigated under various bias and thermal stressing conditions through BTS analysis. Stressed samples are analyzed with high frequency C-V curves, and time-of-flight secondary ion mass spectrometry depth profiles. From the results, the 5 nm Ta barrier is proved to be stable in the Cu interconnect system. (C) 2004 American Vacuum Society.