A study was carried out to determine the feasibility of using the Cu electroplating process to achieve good gap fill in interchip-via (ICV) wafers, focusing on the effect different current wave forms have on electroplated Cu film properties, the gap fill capability and the chemical mechanical planarization process. It was found that the roughness of direct current (dc)-plated Cu films is at least three times lower than that of pulse-plated films and the roughness of the latter was observed to be strongly dependent on the magnitude of forward (I-f) and reverse (I-r) currents. This produced a significant difference in reflectivity between the two types of films. The as-deposited dc- and pulse-plated Cu films were also found to have specific resistivities of similar to2.2 and similar to2.1 PSI cm, respectively. They were reduced to a similar value of 1.77 muOmega cm after annealing at 200 degreesC. All the dc and higher I-f pulse-plating processes produced Cu films having an average polish rate of 7000 Angstrom/min with the polish rate U% less than 3%, showing a fluctuating profile across the wafer. The higher I-r pulse-plated film showed a very low polish rate of 210 Angstrom/min with the polish rate U% at 58%, resulting in a dome profile. The multistep dc plating process was found unsuitable for the filling of large vias in the ICV wafers as it resulted in conformal plating with a large center seam being seen due to the pinch-off effect at the top of the via. The pulse-plating process showed a significant improvement in the gap fill capability with a reduction in the size of the center void. The pinch-off effect was also greatly reduced when higher I, was used and an increase in bottom coverage could also be seen, resulting in acceptable gap fill with only a small center void in the ICV wafers. (C) 2004 American Vacuum Society.