Mapping, with nanometer-scale precision, overlay errors, and other pattern errors, is obviously needed in the development of any patterning technology, and the electrical test structures for this purpose have been commercially available for some time. In prior work [M. W. Cresswell, M. Gaitan, R. A. Allen, and L. W. Linholm, Proc. IEEE 4, 129 (1991)], it was pointed out that the nonzero width of the voltage taps introduced errors but that these could be compensated using a modified structure. We have designed, built and evaluated simple voltage dividing potentiometers with narrower taps to minimize the earlier errors and the mapping pattern errors are within a few nanometers. Our preliminary devices have tap widths of 200 nm. The test structures are implemented in 80 nm An on 5 nm Ti on an oxidized silicon wafer and the measurements of displacement between -100 and 100 nm were made with a precision better than 10 nm. (C) 2004 American Vacuum Society.